rev. 0 an-686 application note one technology way p.o. box 9106 norwood, ma 02062-9106 tel: 781/329-4700 fax: 781/326-8703 www.analog.com implementing an i 2 c ? reset by jim greene the i 2 c bus is a high integrity, robust serial bus used for control purposes in many systems. the primary compo- nents that make up a system are at least one master and one slave. under normal conditions, everything works ne; however, it is the abnormal conditions that gener- ate problems. two questions present themselves when a problem arises: is the problem device or system related, or some combination of both? what, if anything, can be done about it? hard device failures are relatively easy to isolate. perhaps a function does not work, proper power cycling does not resolve the issue, pins are stuck high or low, and so on. system related problems sometimes disguise themselves as device failures, or worse, are intermittent. it is the latter area that this application note examines because it repre- sents the majority of bus fault conditions. pe rhaps a brief description of the i 2 c bus is in order. the i 2 c (inter integrated circuit) bus was developed and pat- ented by philips. it allows devices to communicate over an open-drain (or open-collector) 2-wire serial bus. inter- facing is simple; serial data (sda) and serial clock (scl) are the only signals that traverse the circuit board. due to the low speed (literally dc to 400 kb/s) problems associ- ated with routing, transmission line effects and matching are nonexistent. the limiting factor is bus capacitance, which is limited to 400 pf. the following terms are used to describe the i 2 c bus: master ?he device that initiates a message, and de nes the direction of the i 2 c bus. the master is also responsible for the generation of the clock (scl). (9 clocks per byte: 8 for data and 1 for the acknowledge.) slave ? device with an address that is addressed by a master. start ? bus condition in which the scl line is high and the sda line transitions from a high to a low. it is the rst operation on the bus and is always followed by an address. the least signi cant bit determines the direc- tion of the bus. a high tells the slave that the bus will read, while an lsb = 0 identi es a write to the speci ed address. stop ?he condition opposite start, under which the scl line is high while the sda line goes from a low to a high state. it is the only method of ending a transmission after the reception of a byte. byte width ?ll bytes are 8 bits wide, with no exceptions. message length ?echnically there is no maximum length for a message; a minimum message consists of 2 bytes (an address and a data byte). wait state ?his condition is rarely used, but is worth understanding. once the scl line is low, a device may continue to hold it low to identify a wait state. the wait state permits slow devices to not lose synchronization with the transmitting device. an example is writing many bytes to an e 2 prom; another is a processor holding off data from a slave to handle an interrupt. acknowl edge ?he ack?is the condition under which the master generates a 9 th clock pulse on the scl line (for each byte) while the receiving device pulls the sda line low in order to signify that the last byte was received. a ?ak?is only generated by the master; it signals the slave that no additional data need be sent. a nak is used prior to a stop to prevent the slave from driving the bus with additional data when the master is about to termi- nate the communication. fr equently the master, which is usually a microcontroller or a gate array, will be interrupted in the middle of its communication with an i 2 c slave and, upon return, nd a stuck bus. initially this looks like a device problem, but it is not. the slave is still waiting to send the remainder of the data requested by the master. the problem is that the master has forgotten where it was when it was inter- rupted or reset. an extraneous reset on the processor will generally create this condition, especially if the processor cannot save its status. at this point, the slave will have put the next bit out on the sda line (because the scl line may have dropped to a low on reset) and awaits the next clock on scl. of course the processor does not send it, and as a result this slave just waits and waits. if the bit the slave puts on the sda line is a 0, the newly awakened processor sees what appears to be a hung bus. the bus is in a nonoperational mode; however, it is not due to the slave. it is the processor s fault for not nishing the mes- sage it started. generating graceful resets is not within the scope of this application note.
rev. 0 e04536e0e12/03(0) an-686 e2e ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owne rs. what should you do? the slave must be permitted to t n- ish sending this last byte or be reset externally. solution 1: clocking through the problem the t rs t solution (letting the slave t nish) requires no additional hardware because it is implemented in software. note that while this method is very effective, it may not be possible to clear a hung bus on every manufacturer?s device all the time. (the design of the i 2 c state machine will determine the effectiveness of the clocking approach.) the method is quite simple. it is the master?s job to recover the bus and restore control to the main program. when the master detects the sda line stuck in the low state, it merely needs to send some additional clocks and gener- ate a stop condition. how many clocks will be needed? the number will vary with the number of bits that remain to be sent by th e slave. the maximum would be 9. this number is derived from the worst-case scenario, the case where the processor was reset just after sending an ack to the slave. now the slave is ready to send 8 data bits and receive 1 ack (or nak in the case of a bus recovery). the procedure is as follows: 1) master tries to assert a logic 1 on the sda line 2) master still sees a logic 0 and then generates a clock pulse on scl (1-0-1 transition) 3) master examines sda. if sda = 0, go to step 2; if sda = 1, go to step 4 4) generate a stop condition note that this process may need to be repeated because the cleared sda line may have been cleared for the next bit, which was a 1. there may be some concern about the effect this additional clocking and stopping has on other peripherals. there is no adverse effect; other slaves are not paying attention due to the fact that they have not been addressed. only the slave that had the interrupted message will respond to the clocks. this procedure is useful in the system code to help re- store the bus in the event that an sda = 0 bus fault is encountered, regardless of the reason. solution 2: adding a reset pin to an i 2 c slave another method will reset the i 2 c slave. one function never seen on an i 2 c slave is a reset pin. to remedy this type of problem, a reset function is added via additional hardware: an analog switch. the analog switch needs several attributes to perform the reset function properly. the adg749 t lls the requirements: small package: the sc70 requires less than 5 square mm of board space spdt switch with break-before-make action ve ry low on resistance: 3.5 at 5 v and 4.5 at 3 v excellent on resistance ? atness (allows repeatable resets in digital devices) at 1 a of supply current, the power budget is not affected the diagram below shows how the adg749 can provide a reset to an i 2 c slave device. when a reset to the slave must occur, the processor sends a logic low to the control pin on the analog switch now labeled reset (see diagram). the low going reset pulse must be of suft cient width to permit the switch to discharge the decoupling capacitors and internal circuitry. the adg749 is capable of generat- ing a reset to many i 2 c devices with their associated decoupling capacitors. testing has shown that a 15 s reset pulse will switch the v dd line of 2 slaves and 1 f of capacitance to within 0.1 v of ground in <10 s. the turn on time is equally impressive at <5 s, which means that the i 2 c state machine will reset itself on power up. with an operational voltage range of 1.8 v to 5.5 v, the adg749 permits literally any i 2 c device to be reset by the processor. analog devices has other analog switches if level translation functions are required. note: switch shown with reset s s ee reset figure 1. simple interface resets i 2 c bus pu rchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c p atent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specit cation as det ned by philips.
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